Differential logic gates have a wide range of applications. Clock generation circuits, for example, provide an excellent application for which differential logic gates can be used. Clock generation circuits implemented with differential logic gates have the capability of significantly reducing the clock skew and jitter over an equivalent design implemented with single-ended logic families. In fact, any application, which requires superior noise immunity, is especially suited for differential logic implementations. Differential inputs used in differential logic families promote common mode rejection of cross talk noise and EMI radiation.
Differential logic gates, however, can exhibit undesirable characteristics as well. Propagation delay exhibited by some prior art differential logic families is one such unattractive characteristic. Most of the propagation delay of differential logic gates can be attributed to the switching delay of each transistor in the differential pair. Each transistor of the differential pair is either in a conductive state or in a non-conductive state, depending upon the level of the logic applied to their respective control terminals. Time required to transition the transistor from a conductive state to a non-conductive state or vice versa is known as the switching delay. As the transistors transition between conduction states, the gain of the transistors also change, which causes ringing on the collector output voltages when the transistors are exhibiting high gain. As the gain changes on prior art differential logic gates, the input impedance also changes which creates difficulty when using controlled impedance transmission paths.
Referring to FIG. 1, an improved prior art differential logic circuit 10 is illustrated which provides one method of reducing switching delays induced by toggling the conduction states of differential input transistor pairs by using cascode amplifiers. Transistors 12 and 14 provide a cascode amplifier arrangement such that the voltage variation at nodes 26 and 28 is reduced. Reducing voltage variation at nodes 26 and 28 reduces the miller capacitance effect seen at terminals D and D-compliment, which reduces switching delays through prior art differential logic circuit 10. Voltage variation at nodes 26 and 28 can be further reduced by the addition of keep alive current sources 16 and 18. Keep alive current sources 16 and 18 provide a nominal amount of current flowing through cascode amplifiers 12 and 14 regardless of the conduction state of transistors 20 and 22, respectively. Sizing the keep alive current sources 16 and 18 such that current conduction through transistors 16 and 18 is a substantial portion of the total current entering nodes 26 and 28, respectively, the corresponding voltage variation at nodes 26 and 28 can be significantly reduced, thus substantially eliminating the miller effect. As logic families develop, however, the required input logic voltage swings diminish which inherently diminishes the magnitude of the miller effect. Additionally, as logic families develop, the top supply rail potential diminishes which requires reducing the number of base-emitter voltage (V.sub.be) drops between top and bottom supply rail potentials. New logic families, therefore, no longer have the top supply rail potential headroom to support a cascode amplifier configuration to reduce the miller effect.
A need exists, therefore, for a differential logic gate, which provides reduced switching delay, reduced ringing and improved input impedance control without the need for an additional cascode amplifier configuration.